Take charge of the Metal process optimization and development of advanced nodes (5nm & beyond)

Take charge of the Dielectric process optimization and development of advanced nodes (5nm & beyond)

1. To collaborate with TSMC internal teams for Die to Die IO solution offering. 2. To define/design GPIO library ESD/electrical spec to meet 3DIC package requirement, including InFO or CoWoS or SoIC. 3. To define GPIO ...

Role: Lead the Embedded Memory Product Engineering team to ensure production ready(5nm~16nm) Responsibilities: 1.SRAM bitcell development/improvement in technology ramp-up and volume-production. 2.SRAM compiler/IP ...

- Define standard cell circuit requirement and complete design from schematic, layout and verification. - Conduct schematic design of deep-submicron CMOS technologies using industrial standard simulation tool, such as ...

Chip/Block level floorplan, Clock tree synthesis, Place & Route, RC extraction, STA, timing closure, IR/EM analysis and fix, DRC/LVS/ERC analysis and fix, Tape-out sign off. APR Flow development ...

1. Physical implementation of advanced technology chips. 2. Be responsible for chip implementation and signoff closure of customer’s projects or internal system test chips. 3. Be Familiar with design methodology ...

● Perform the following: o Chip/Block level floorplan o Clock tree synthesis o Place & Route o RC extraction o STA, timing closure o IR/EM analysis and fix o DRC/LVS/ERC analysis and fix o Tape-out sign off

Job Role: Analog Cell Development and Automation Analog cell related software support PDK delivery Design flow transformation Design automation

- Define and implement standard cell characterization methodology for leading edge technology. - Path finding and innovation of new cell and/or new feature characterization. - Define sub threshold voltage ...

The role is responsible for providing engineering services to a key North American account. 1. Handle customer's tapeouts and prototyping requests. 2. Prepare and host customer meetings and visits, and follow up ...

● RDR design rules optimization. ● Develop Standard Cell/IO Library Memory and Analog IPs in advanced technology. ● Develop Memory IPs, Compiler and Test Vehicle. ● Develop Standard Cell/IO Library and Analog. IPs ● ...

Job RoleDevelop strategies, execute commercial deals and drive end user adoption.Job Responsibility1. Drive strategic EDA tool adoption/migration in sync with overall marketing strategy.2. Drive Cloud business ...

Memory architecture design (SRAM, DRAM, MRAM, RRAM, PCRAM and eFlash) Read and write critical path design and analysis Design of key building blocks (sensing, analog, high voltage, DFT) Chip-level design ...